SiP(System in Package) LSI of; Single-Chip Digital Servo Processor incorporating CDHead Amplifier/CompressionAudioDecoder and 16Mbit DRAM for ESP(Electrical Shock Proof) function.

The TC94B14MFG is a single chip processor which incorporatesthe following functions:CD Head amplifier, EFM synchronous signal separation protection and interpolation, EFM demodulation, error correction,microcontroller interface, servo-use digital equalizer and servocontrol circuit, multi bit DA converter and Compression audiodecoder firmware such as for MP3, WMA , MPEG4-AAC and 16Mbit DRAM for ESP.The TC94B14MFG makes it possible to configure a CD-MP3 player with ESP quite easily with an adjustment-free basis.

Common to all sections
Operation Supply Voltage : CD, I/O, DAC:3.0 – 3.6V,
DSP Logic, 1MbitSRAM:1.4-1.6V
Stand-By function:Hold the data stores in 1MbitSRAM supplying the Voltage only to 1MbitSRAM
Operation Temperature : - 20 ~ 70 °C
Package, LQFP-80, Pin pitch 0.5 mm
Micro controller interface: 4bit parallel interface( 6 lines),
CMOS silicon Monolithic LSI
[Head amplifier section]
CD-DA/R/RW : up to x2 speed.
Built-in reference voltage (VRO) generation circuit.
Built-in APC (auto laser power control) circuit.
Built-in RF signal generation circuit.
Enables the polarity of the offset voltage correction of the RF signal to be switched.
Built-in AGC (auto gain control) circuit for the RF signal. (gain adjustment range of ±6 dB)
Built-in RF equalizer correction circuit.
Built-in focus error signal and tracking error signal circuits.
Built-in signal generation circuit for track counting(RFRP).
Built-in circuit for generating a sub beam addition signal or an RFDC signal, whichever is selected, as a defect.
detection signal. (Note that the RFDC signal is supported only when the RFO signal is positive.)
Supports DC offset correction functions (for focus, tracking, and RF sections).
Supports both CD-DA and CD-R/RW modes.
Supports a voltage output type pickup.
[Digital servo processor section]
Capable of decoding text data (CD-TEXT mode 4).
Capable of performing sync pattern detection, sync signal protection and interpolation securely.
Built-in EFM demodulation circuit and sub code demodulation circuit
Has a jitter absorbing capacity be switched among ±6 frames and ±22 frames.
Capable of making double C1 correction and quadruple C2 correction, using CIRC correction logical expressions.
Built-in 64Kbit RAM
Built-in digital attenuators
Enables audio outputs to be switched among 32 fs, 48 fs, and 64 fs.
Capable of reading sub code Q data at any time and outputting it in synchronization with audio data.
Built-in data slice circuit (analog/digital slicing) and compensation circuit
Built-in analog PLL (with an adjustment-free VCO)
Uses an active wide-range PLL system.
Supports variable-speed playback.
Supports CLV modes (for up to ×2 speed)
Supporting automatic loop gain, offset, and balance adjustments for focus and tracking servo sections.
Built-in RF gain automatic adjustment circuit
Built-in digital equalizer
Built-in digital equalizer coefficient RAM, supporting various pickup types
Built-in focus and tracking servo control circuits
Supports all search control modes, thus realizing high-speed stable searches.
Uses speed-controlled lens kick and feed kick.
Built-in AFC and APC circuits for disc motor CLV servo control
Built-in anti-defect and anti-shock circuits
Support Stepper Motor
[Audio DSP section]
Incorporating f

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